Member of the VLSI design team developing
integrated ICs for the consumer market. The team owns design,
verification and maintenance of all internal units in the chip under
development and is responsible for the full chip flow as well. Performs
micro architecture definition, verification plan definition, RTL design
and verification, synthesis and static timing analysis. Responsible for
all DFT aspects of the design flow, from unit to full chip level. This
includes handling of boundary and internal scan insertion and ATPG,
MBIST development, test modes and test mux management, production test
strategy development and formal verification. Interfaces with customers
in regards to future product requirements and current product
enhancements. Interact with all design groups providing consultation,
direction and review.
- Must have an engineering degree Electronic Engineering or Computer Engineering.
- At least 3 years of experience with ASIC design.
- Hands on experience with all relevant VLSI design tools.
- Verilog RTL programming skills.
- Synthesis (Design-Compiler or Ambit).
- Experience with Simulation (NCV or VCS).
insertion (Test-Compiler or DFT-Advisor), ATPG (Fastscan or Tetramax)
and formal verification (Formality or Verplex), Static Timing Analysis
(PrimeTime or Pearl).
- Should have exposure and good understanding of back-end design flow.
- Excellent communication skills in Hebrew and English (written and verbal) and good interpersonal skills.
- Experience with video and SoC systems.
- Knowledge of verification methodologies and advanced verification tools (such as - VERA code coverage, assertion based testing).
- Experience with embedded IP cores testing.
- Experience with PCI bus interface, and with hardware debugging tools such as Logic Analyzers and Scopes.
University grades pre-requisite
- Technion/Tel-Aviv University graduates GPA over 80.
- Other Universities, GPA over 90.
The position applies for both men/women.
Please send potential applicant's CV's to: