Member of the VLSI backend design team
developing integrated ICs for the consumer electronics market. The team
owns backend design, verification and maintenance of all internal units
in the chip under development and is responsible for the full chip
backend flow as well.
Responsible for IC backend design, including floorplanning, power grid,
place & route, clock tree insertion, scan insertion, physical
verification, signal integrity verification, timing closure, and
- Must have an Electronic Engineering degree.
- At least 3 years of experience with backend design.
on experience with all relevant VLSI backend design tools such as
Synopsys Astro or Cadence FE, Mentor , LEC, DRC and LVS check.
in complete physical design flow gate-level netlist to GDSII -
preferably in Astro PC flow - including CTS, design partitioning &
floor planning, Place & Route, Physical verifications, Parasitic
extraction, DRC/LVS/Antenna & Signal Integrity Closures, ECO
handling & reliability analysis both at module and chip level.
- Excellent knowledge of floor planning, macro placements, PG grid generations, on chip memory, analog macro integrations etc.
- Excellent knowledge of timing driven placement techniques & post layout STA, EBS, layer generation.
- Excellent theoretical & working knowledge of Power Analysis, Electro migration, IR drop & Xtalk analysis.
- Excellent knowledge of advanced electrical & reliability analysis in deep sub-micron technologies.
- Excellent background/knowledge of CMOS, BiCMOS etc.
& expertise in Shell, Perl, TCL/TK scripting & complete
familiarity with design & verification tools is a must proficiency.
- Familiar with the design file types such as LEF, DEF, SDF, and GDS.
in at least 2 successful tapeouts of large ICs (die-size larger than
80sq. mm.), at least one of them to TSMC using 0.13u technology or
- Excellent communication skills in Hebrew and English (written and verbal) and good interpersonal skills.
- Experience with mixed signal layout.
- Experience with video and SoC systems.
- Experience with embedded IP cores testing.
University grades pre-requisite
- Technion/Tel-Aviv University graduates GPA over 80.
- Other Universities, GPA over 90.
The position applies for both men/women.
Please send potential applicant's CV's to: